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Actalent
bangalore
Title: Design Engineer Position Reports To: Manager Location: Bangalore, Pune Immediate joiners preferred with 0-30 days' notice period. Job Requirements: 2 to 5 Years’ experience in BIW fixture 3D concept design & 2D Finish. CAD Software: NX /CATIA V5/Fides Understand BIW process information & overall tool functionality (all types of tools Perf
Job Source: ActalentideaForge
bangalore
Job Title Sr System Integration Engineer Department Mobility Solutions Job Description At ideaForge, we are a leading drone technology company focused on developing innovative unmanned aerial systems. We specialize in designing and manufacturing high-performance drones for various industries, including aerial photography, surveillance, logistics, a
Job Source: ideaForgeUST GLOBAL TECHNOLOGY SERVICES (INDIA) PRIVATE LIMITED
bangalore
Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physi
Job Source: UST GLOBAL TECHNOLOGY SERVICES (INDIA) PRIVATE LIMITEDTech Mahindra
Bengaluru, Karnataka, India
Hi Folks Greetings from Tech Mahindra!! Role: STA Exp: 4 -8 Location: Bangalore/ Kochi/ Ahemdabad / Vizag About Job Deep understating and experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO) . Knowledge of timing corners/modes, process variations and signal integrity related issues are required. Experience in timing closure of high frequ
Job Source: Tech MahindraChubb
bangalore
The Purpose of the role As a key member of the Advanced Analytics and Digital team, he/she will be at the foreftont of developing new innovative data driven solutions with bleeding edge machine learning algorithms. AI Data Scientist is a technical job that uses machine learning techniques to automate underwriting processes. This person will be work
Job Source: ChubbL&T Technology Services
Bengaluru
STA Engineer with 5+ years’ experience Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure technique
Job Source: L&T Technology ServicesACL Digital
Bengaluru
Work Location: BangaloreSkills :4+ years of experience in STA.Well-versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C mod
Job Source: ACL DigitalUST GLOBAL TECHNOLOGY SERVICES (INDIA) PRIVATE LIMITED
Bengaluru
Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physi
Job Source: UST GLOBAL TECHNOLOGY SERVICES (INDIA) PRIVATE LIMITEDBengaluru, Karnataka, India
STA Engineers:
Location: Bangalore/Hyderabad/Pune/Noida
Responsibilities
·Ability to work with RTL design team to identify the must changes in RTL to coverage the timing and work with PD teams to analyze the post route timing & support the final timing closure.
Drive the sign-off timing convergence for high performance designs.
Work closely with block owners throughout the project for sign-off timing convergence.
· Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
Preferred Qualification/Skills
Experience in timing analysis/debug and driving the timing convergence for complex blocks & release the netlists to PD team
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Hands-on experience with STA tools - Prime-time/ Tempus
Have experience in driving timing convergence at Chip-level and Hard-Macro level
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
· Hands on experience on constraint development for synthesis from scratch is a plus
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation is a plus
Proficient is scripting languages – TCL, Perl, Awk
STA engineers jobs in Bengaluru, Karnataka, India
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